1. Field of the Invention
The present invention generally relates to an information processing method and an information processing apparatus. More specifically, the present invention is directed to an interrupt control method, and an interrupt control apparatus controlling a plurality of interrupt requests by applying priority orders, or priority degrees to these interrupt requests.
2. Description of the Related Art
When an interrupt process occurs while a main process operation is executed by a processor, this processor temporarily interrupts the main process operation under execution, and executes the interrupt process. In the case that such interrupts are produced in a multiple manner, since the processor cannot simultaneously execute a plurality of interrupts, the processor is required to perform an interrupt control in such a manner that the processor applies priority orders, or priority degrees to these plural interrupts, and then sequentially executes the interrupt processes having the higher priority orders.
A typical interrupt process operation executed by one conventional information processing apparatus is described as follows: FIG. 9 is a schematic block diagram for representing an arrangement of a conventional interrupt control apparatus. FIG. 10 is a timing chart for explaining a control operation executed by this conventional interrupt control apparatus. FIG. 11 is a state transition diagram for indicating state changes in the respective structural arrangement units of this conventional interrupt control apparatus.
As indicated in FIG. 9, the conventional interrupt control apparatus is mainly arranged by an interrupt flag holding circuit 11, an interrupt level holding circuit 12, an interrupt level judging circuit 13, an interrupt factor holding circuit 14, an interrupt vector generating circuit 15, and an interrupt vector holding circuit 16. When an interrupt request is entered, the interrupt flag holding circuit 11 sets a flag in correspondence with the entered interrupt request, and further holds an interrupt level. The interrupt level holding circuit 12 holds an interrupt level of an interrupt request under execution by a processor. The interrupt level judging circuit 13 judges such an interrupt level having a top priority order among the interrupt levels held in the interrupt flag holding circuit 11, and outputs an interrupt factor corresponding thereto. The interrupt factor holding circuit 14 holds the interrupt factor outputted from the interrupt level judging circuit 13. The interrupt vector generating circuit 15 generates such an interrupt vector indicative of an interrupt sort in response to the interrupt factor outputted from the interrupt level judging circuit 13. The interrupt vector holding circuit 16 holds the generated interrupt vector, and outputs the held interrupt vector to the processor 17.
Next, the interrupt processing operation executed in the above-explained conventional information processing apparatus will be described with reference to FIG. 9 to FIG. 11. Since this interrupt processing operation is sequentially advanced every 1 cycle of a clock CLK, state changes of the respective circuits will be explained as to interrupt processing operations for 19 cycles. In the drawings, an IF stage (interrupt flag holding stage) indicates an operation cycle of the interrupt flag holding circuit 11; a PRI stage (interrupt level judging stage) shows an operation cycle of the interrupt level judging circuit 13; a VCT stage (interrupt vector generating stage) represents an operation cycle of the interrupt vector generating circuit 15; and an EXT cycle (interrupt vector output stage) denotes an operation cycle of the interrupt vector holding circuit 16. It should be understood that symbols "pri0" to "pri7" show interrupt priority orders (degrees), and a relationship among these interrupt priority orders is defined by as follows:
pri0&gt;pri1&gt;pri2&gt;pri3&gt;pri4&gt;pri5&gt;pri6&gt;pri7 PA1 a first step for holding a plurality of flags indicative of interrupt factors with respect to the respective interrupt request inputs and also for holding a plurality of interrupt levels representative of priority orders of the interrupt request inputs; PA1 a second step for judging such an interrupt level having a top priority order by checking the held interrupt levels to thereby hold such an interrupt factor having the judged interrupt level, and also for outputting an interrupt request to a processor of an information processing apparatus; PA1 a third step for generating an interrupt vector in response to the held interrupt factor; and PA1 a fourth step for outputting the held interrupt vector to the processor; wherein: PA1 the first to fourth steps are carried out in a pipeline processing manner so as to control the interrupt requests with respect to the processor, whereby when an interrupt request having a higher interrupt level than that of an interrupt request under process is issued, the processor interrupts the interrupt process operation under execution and then executes an interrupt process operation for the higher interrupt level, whereas when the interrupt process operation for the higher interrupt levels is accomplished, the processor clears the interrupt level held in the second step and then restarts the interrupt process operation for the lower interrupt level. PA1 a first step for holding a plurality of flags indicative of interrupt factors with respect to the respective interrupt request inputs and also for holding a plurality of interrupt levels representative of priority orders of the interrupt request inputs; PA1 a second step for judging such an interrupt level having a top priority order by checking the held interrupt levels to thereby hold such an interrupt factor having the judged interrupt level, and also for outputting an interrupt request to a processor of an information processing apparatus; PA1 a third step for judging priority orders based upon default values indicative of sequence numbers of the interrupt request inputs with respect to the held interrupt factors, and also for generating an interrupt vector in response to such an interrupt factor having a top priority order to thereby hold the generated interrupt vector; and PA1 a fourth step for outputting the held interrupt vector to the processor; wherein: PA1 the first to fourth steps are carried out in a pipeline processing manner so as to control the interrupt requests with respect to the processor, whereby when an interrupt request having a higher interrupt level than that of an interrupt request under process is issued, the processor interrupts the interrupt process operation under execution and then executes an interrupt process operation for the higher interrupt level, whereas when the interrupt process operation for the higher interrupt levels is accomplished, the processor clears the interrupt level held in the second step and then restarts the interrupt process operation for the lower interrupt level. PA1 a fifth step for holding an interrupt level of an interrupt request under process by the processor, and also for clearing an interrupt level of such an interrupt request, which has been processed by the processor when an interrupt request acknowledge signal is applied from the processor; wherein: PA1 in the second step, such an interrupt request having a top priority order is judged among the plural interrupt requests having the interrupt levels, which are held in the first step, except for an interrupt request having an interrupt level lower than that of the interrupt request under process by the processor. PA1 interrupt level judging means for judging such an interrupt level having a top priority order by checking the held interrupt levels to thereby hold such an interrupt factor having the judged interrupt level, and also for outputting an interrupt request to a processor of the information processing apparatus; PA1 interrupt vector generating means for generating an interrupt vector in response to the held interrupt factor; and PA1 interrupt vector generating means for outputting the held interrupt vector to the processor; wherein: PA1 the processing operations by all of the means are carried out in a pipeline processing manner so as to control the interrupt requests with respect to the processor, whereby when an interrupt request having a higher interrupt level than that of an interrupt request under process is issued, the processor interrupts the interrupt process operation under execution and then executes an interrupt process operation for the higher interrupt level, whereas when the interrupt process operation for the higher interrupt levels is accomplished, the processor clears the interrupt level held in the interrupt level judging means and then restarts the interrupt process operation for the lower interrupt level. PA1 interrupt level judging means for judging such an interrupt level having a top priority order by checking the held interrupt levels to thereby hold such an interrupt factor having the judged interrupt level, and also for outputting an interrupt request to a processor of the information processing apparatus; PA1 default priority order judging/interrupt vector generating means for judging priority orders based upon default values indicative of sequence numbers of the interrupt request inputs with respect to the held interrupt factors, and also for generating an interrupt vector in response to such an interrupt factor having a top priority order to thereby hold the generated interrupt vector; and PA1 interrupt vector outputting means for outputting the held interrupt vector to the processor; wherein: PA1 the process operations by all of the means are carried out in a pipeline processing manner so as to control the interrupt requests with respect to the processor, whereby when an interrupt request having a higher interrupt level than that of an interrupt request under execution is issued, the processor interrupts the interrupt process operation under execution and then executes an interrupt process operation for the higher interrupt level, whereas when the interrupt process operation for the higher interrupt levels is accomplished, the processor clears the interrupt level held in the interrupt level judging means and then restarts the interrupt process operation for the lower interrupt level. PA1 interrupt level holding means for holding an interrupt level of an interrupt request under process by the processor, and also for clearing an interrupt level of such an interrupt request, which has been processed by the processor when an interrupt request acknowledge signal is applied from the processor; wherein: PA1 the interrupt level judging means is arranged in such a way that an interrupt request having a top priority order is judged among the plural interrupt requests having the interrupt levels, which are held in the interrupt level holding means, except for an interrupt request having an interrupt level lower than that of the interrupt request under process by the processor. PA1 interrupt request input series are connected to an input of the first circuit group and arranged in such a manner that the priority orders of the default values are sequentially changed, wherein: PA1 an interrupt vector corresponding to such an interrupt request having a top priority order of a default value among the default values of the interrupt request input series is outputted from a final stage of the third circuit group as a signal having a bit number corresponding to a total input number of the interrupt request input series. PA1 the second circuit group is constituted by a second OR gate circuit for OR-gating the two interrupt requests OR-gated by two sets of the first adjoining OR gate circuits employed in the first circuit group, a second AND gate circuit for AND-gating the two interrupt requests AND-gated by two sets of the first adjoining AND gate circuits, and also a first selector for selecting one of the interrupt requests AND-gated by the two first adjoining AND gate circuits to output an AND-gated interrupt request having a higher priority order in response to the output from the first OR gating circuit; and such a circuit for outputting signals in a parallel manner, while defining the output from the second AND gate circuit as an upper digit of the signal and the output from the first selector as a lower digit thereof is connected to the output of the first circuit group; and PA1 the third circuit group is constituted by a third OR gate circuit for OR-gating the two interrupt requests OR-gated by two sets of the second adjoining OR gate circuits employed in the second circuit group, a third AND gate circuit for AND-gating the two interrupt requests AND-gated by two sets of the second adjoining AND gate circuits, and also a second selector for selecting one of the interrupt requests AND-gated by the two second adjoining AND-gate circuits to output signals containing the AND-gated output of the two second AND gate circuits as an upper digit thereof and the output of the first selector as a lower digit thereof in response to an OR-gated interrupt request having a higher priority order; and such a circuit for outputting signals in a parallel manner, while defining the output from the third AND gate circuit as an upper digit of the signals and the output from the second selector as a lower digit thereof is connected to the output of the first circuit group in a reverse tree-structure.
The interrupt processing operations of the conventional information processing apparatus are executed in accordance with the following cycles:
(1) 1st Cycle
Assuming now that an interrupt request having a priority order "pri7" is issued in any one of interrupt request inputs INT-0 to INT-x under such a condition that all of the contents of the interrupt flag holding circuit 11 and of the interrupt level holding circuit 12 are cleared, a flag is set to the interrupt flag holding circuit 11 in the IF stage (this state is indicated as "IF7").
(2) 2nd Cycle
Next, in the PRI stage, the interrupt level held in the interrupt flag holding circuit 11 is read, and the read interrupt level is judged by the interrupt level judging circuit 13. At such a present time when only one interrupt request is issued, since the priority order pri7 is the highest order, the interrupt factor of pri7 is held in the interrupt factor holding circuit 14, and also an interrupt request "REQ" based upon pri7 is outputted to the processor 17 from the interrupt level judging circuit 13 via an interrupt request signal line INTRQ (this state is indicated as "PRI7"). At this time, since an interrupt request having a priority order "pri6" is issued, a flag is set to the interrupt flag holding circuit 11 in the IF stage (this state is indicated as "IF6").
(3) 3rd Cycle
While the interrupt request REQ based on pri7 is issued from the interrupt level judging circuit 13 to the processor 17, this processor 17 is set to such a state for rejecting the interrupt request REQ based on pri7. At this time, at a VCT stage, the interrupt vector generating circuit 15 generates an interrupt vector by the interrupt factor read from the interrupt factor holding circuit 14, and the generated interrupt vector of pri7 is held in the interrupt vector holding circuit 16 (this state is indicated as "VCT7"). Also, in the IF stage, since an interrupt request having a priority order of "pri5" is issued, a flag is set to the interrupt flag holding circuit 11 (this state is indicated as "IF5").
(4) 4th Cycle
Subsequently, while the interrupt request REQ based on pri7 is issued from the interrupt level judging circuit 13 to the processor 17, this processor 17 is set to such a state for rejecting the interrupt request REQ based on pri7. At this time, at an EXT stage, the interrupt vector based upon pri7 held in the interrupt vector holding circuit 16 is read to an interrupt vector signal line INTLV (this state is indicated as "EXT7"). Also, in the IF stage, since an interrupt request having a priority order of "pri4" is issued, a flag is set to the interrupt flag holding circuit 11 (this state is indicated as "IF4").
(5) 5th Cycle
Subsequently, the interrupt request REQ based upon pri7 is outputted from the interrupt level judging circuit 13, and further an interrupt vector based on pri7 held in the interrupt vector holding circuit 16 is read. Since the processor 17 is capable of executing an interrupt process operation, this processor 17 can accept an interrupt request REQ with respect to this interrupt. At this time, since the interrupt request based upon the priority order of "pri1" is issued, a flag is set to the interrupt flag holding circuit 11 in the IF stage (this state is indicated as "IF1").
(6) 6th Cycle
Subsequently, the interrupt request REQ based upon pri7 is outputted from the interrupt level judging circuit 13, and also the interrupt vector bases on pri7 held in the interrupt vector holding circuit 16 is read. The processor 17 samples the interrupt vector based on pri7 to branch the sampled interrupt vector to a target. The processor 17 commences an interrupt service of pri7 by performing an interrupt process operation in an interrupt process routine, and further returns an interrupt acknowledge AK to the interrupt flag holding circuit 11 via an interrupt acknowledge signal line INTAK. As a result, the interrupt flag based on pri7 held in the interrupt flag holding circuit 11 is cleared, and also the interrupt level having the priority order of pri7 held in the interrupt level holding circuit 12 is cleared. At this time, in the IF stage, since an interrupt request having a priority order of "pri3" is issued, a flag is set to the interrupt flag holding circuit 11 (this state is indicated as "IF3").
(7) 7th Cycle
The interrupt levels of the interrupt requests except for the interrupt request based on pri7 are read from the interrupt flag holding circuit 11, and then these read interrupt levels are judged by the interrupt level judging circuit 13. Since the priority order of pri1 is the highest priority order, the interrupt factor of pri1 is held in the interrupt factor holding circuit 14, and further an interrupt request REQ based upon pri1 is outputted from the interrupt level judging circuit 13 (this state is indicated as "PRI1"). The processor 17 continues the service of the interrupt based on pri7. At this time, since no interrupt request is issued, the state of the interrupt flag holding circuit 11 is not changed in the IF stage (this state is indicated as "IF").
(8) 8th Cycle
Subsequently, the interrupt request REQ based on pri1 is outputted from the interrupt level judging circuit 13 to the processor 17, and also an interrupt vector is generated by the interrupt vector generating circuit 15 based upon the interrupt factor read from the interrupt factor holding circuit 14. Then, the generated interrupt vector based on pri1 is held into the interrupt vector holding circuit 16 (this state is indicated as "VCT1"). At this time, since an interrupt request having a priority order of "pri0" is issued, a flag is set to the interrupt flag holding circuit 11 in the IF stage (this state is indicated as "IF0").
(9) 9th Cycle
Subsequently, the interrupt request REQ based upon pri1 is outputted from the interrupt level judging circuit 13, and also the interrupt vector based on pri1 held in the interrupt vector holding circuit 16 is read (this state is indicated as "TXT1"). The processor 17 continues a service corresponding to the interrupt of pri7. At this time, since an interrupt request having a priority order of "pri2" is issued, a flag is set to the interrupt flag holding circuit 11 in the IF stage (this state is indicated as "IF2").
(10) 10th Cycle
Subsequently, the interrupt request REQ based upon pri1 is outputted from the interrupt level judging circuit 13, and also the interrupt vector based on pri1 held in the interrupt vector holding circuit 16 is read. Since processor 17 is capable of the interrupt process, the processor 17 can accept the interrupt request REQ with respect to the interrupt of pri1. Thereafter, since the interrupt request is not issued, the state of the interrupt flag holding circuit 11 is not changed at the IF stage (this stage is indicated as "IF").
(11) 11th Cycle
Subsequently, the interrupt request REQ based upon pri1 is outputted from the interrupt level judging circuit 13, and also the interrupt vector based on pri1 held in the interrupt vector holding circuit 16 is read. The processor 17 samples the interrupt vector based on pri1 to commence an interrupt service of pri1. The processor returns an interrupt acknowledge AK to the interrupt flag holding circuit 11 via the interrupt acknowledge signal line INTAK. As a result, the interrupt flag based on pri1 held in the interrupt flag holding circuit 11 is cleared, and also the interrupt level having the priority order of pri1 held in the interrupt level holding circuit 12 is cleared.
(12) 12th Cycle
In this cycle, while the interrupt request REQ based on pri0 is outputted from the interrupt level judging circuit 13 to the processor 17, this processor 17 continues the interrupt service of pri1. The interrupt levels of the interrupt request based on pri1 are read from the interrupt flag holding circuit 11, and then these read interrupt levels are judged by the interrupt level judging circuit 13. Since the priority order of pri0 is the highest (top) priority order, the interrupt factor of pri0 is held in the interrupt factor holding circuit 14 (this state is indicated as "PRI0").
(13) 13th Cycle
Subsequently, the interrupt request REQ based upon pri0 is outputted from the interrupt level judging circuit 13 to the processor 17, and also the processor 17 continues the interrupt service of pri1. The interrupt vector is generated based on the interrupt factor read from the interrupt factor holding circuit 14, and then the generated interrupt vector of pri0 is held in the interrupt vector holding circuit 16 (this state is indicated as "VCT0").
(14) 14th Cycle
Subsequently, the interrupt request REQ based upon pri0 is outputted from the interrupt level judging circuit 13 to the processor 17, and also the processor 17 continues the interrupt service of pri1. The interrupt vector of pri0 held in the interrupt vector holding circuit 16 is read (this state is indicated as "EXT0").
(15) 15th Cycle
Subsequently, the interrupt request REQ based upon pri0 is outputted from the interrupt level judging circuit 13 to the processor 17, and also the processor 17 continues the interrupt service of pri1. The interrupt vector of pri0 is held in the interrupt vector holding circuit 16 is read.
(16) 16th Cycle
Subsequently, in this cycle the interrupt request REQ based upon pri0 is outputted from the interrupt level judging circuit 13, and also the processor 17 can execute the interrupt process operation. As a result, the processor 17 can accept the interrupt request REQ with respect to the interrupt of pri0. Also, the read vector of pri0 held in the interrupt vector holding circuit 16 is read.
(17) 17th Cycle
Subsequently, in this cycle, the interrupt request REQ based upon pri0 is outputted from the interrupt level judging circuit 13, and also the interrupt vector base on pri0 held in the interrupt vector holding circuit 16 is read. The processor 17 samples the interrupt vector based on pri0 to commence an interrupt service of pri0, and further returns an interrupt acknowledge AK to the interrupt flag holding circuit 11. As a result, the interrupt flag based on pri0 held in the interrupt flag holding circuit 11 is cleared, and also the interrupt level having the priority order of pri0 held in the interrupt level holding circuit 12 is cleared.
(18) 18th Cycle
In this cycle, the interrupt request REQ based upon pri2 is, outputted from the interrupt level judging circuit 13 to the processor 17, and also the processor 17 continues the interrupt service of pri0. The interrupt levels of the interrupt requests except for the interrupt request based on pri0 are read from the interrupt flag holding circuit 11, and then these read interrupt levels are judged by the interrupt level judging circuit 13. Since the priority order of pri2 is the highest priority order, the interrupt factor of pri2 is held in the interrupt factor holding circuit 14 (this state is indicated as "PRI2").
(19) 19th Cycle
Subsequently, in this cycle, the interrupt request REQ based upon pri2 is outputted from the interrupt level judging circuit 13 to the processor 17, and also the processor 17 continues the interrupt service of pri0. The interrupt vector is generated based on the interrupt factor read from the interrupt factor holding circuit 14, and then the generated interrupt vector of pri2 is held in the interrupt vector holding circuit 16 (this state is indicated as "VCT2").
However, the above-explained conventional information processing apparatus has a problem that the interrupt response characteristic with respect to the interrupt requests having the high priority orders is deteriorated.
This reason is as follows. In this conventional information processing apparatus, when the interrupt factor is applied, the interrupt control apparatus judges the priority orders. When the judgement of the priority orders is accomplished by the interrupt control apparatus, this interrupt control apparatus outputs the interrupt request signal to the processor, and thereafter generates the interrupt vector. At this time, the interrupt state is maintained in order that the interrupt priority orders are not changed. Since maintaining such an interrupt state, the corresponding relationship between the inputted interrupt requests and the outputted interrupt vectors can be established. Also, the judgement of the priority orders and the generation of the interrupt vectors need not be carried out within 1 clock.
However, even when such an interrupt which is applied after the interrupt factor has been defined owns a higher priority order than that of the defined interrupt factor, the first-mentioned interrupt having the higher priority order cannot be accepted until the once defined interrupt is accepted by the processor. As a consequence, the interrupt vector sampled by the processor corresponds to such an interrupt vector when the interrupt control apparatus has outputted the interrupt request signal to the processor before the processor will sample this interrupt vector. Therefore, a problem that results is the delayed processing of the higher priority interrupt.